CALBLOCK-PV-027: VIS Trap Pumping¶
Parent requirement¶
P-R-NI-CAL-PV-001 in EUCL-MPIA-RD-1-001 (CalCD-B)
Observation configuration file¶
Scheduling¶
Repeat each block (see below) twice during PV phase for CR rejection.
The Trap Pumping CALBLOCK is split into 3 variants: VTP-CI-high, VTP-CI-low and STP.
The VTP consists of two variants, corresponding to the CI levels: VTP-CI-high (DAC_IG1=4V) and VTP-CI-low (DAC_IG1=4.75V).
A single VTP-CI-high (or VTP-CI-low) block is split into 4 parts, corresponding to the “234”, “123”, “341”, “412” VTP shuffle modes. Each mode consists of 11 VTP sequences with various trap pumping parameter settings, headed by a Charge Injection (zero shuffle) reference. Hence there are (11+1) x 4 = 48 VTP sequences (44 unique VTP sequence plus 4 CI references) per variant-block, which are doubled in PV execution. Note that the group of 12-VTP-sequence must be executed uninterrupted.
The VTP variant blocks shall be interleaved by a single BIAS, so that there is one BIAS acquired every 6 hours (or less). This results in total of 4 BIASes acquired for the VTP variants.
The STP variant consists of 12 unique Multi-STP sequences. A single STP block consists of a doubling of the 12 sequences (STP01-12), each sequence headed by a single BIAS. The STP block is to be executed twice, in proximity to the VTP variants.
All STP sequences must be followed by 3x throw-away “trash” biases. The reason is as follows: To mitigate a bug in the FPGA, Serial Trap Pumping sequences execute a soft ROE reset at the end, which in turn causes a ~1 ADU bias asymetry in the CCD top and bottom halves of the following image. While the 1 ADU bias asymmetry does not affect the STP analysis (due to the high charge injection level), it is evident in Nominal Science images (where a typical sky level is ~20 ADU), and the bias perturbation can be detected at much lower levels for several exposures after the ROE reset. To clear out the worst of the bias perturbation, every STP should be followed by 3x throw-away trash biases.
In case of failure, repeat as soon as possible.
Time-critical¶
The block repetition (for VTP and STP) can be separated within the PV. However, the first VTP blocks (CI-high and low) must be scheduled in proximity to the PV-028, CI-ROS variant. The STP block should be scheduled in proximity to VTP, at a lower priority than the VTP and CI-ROS variant proximity.
Dependencies¶
None
Objective¶
Trap pumping during PV phase will give BoL trap information for the whole focal plane, i.e. a full TOI set in less than a day. This is needed to initialise the trap analysis for the CTI correction.
Observations¶
One set of all frames as defined in CALPRODUCT-VS-025: VIS Trap Pumping.
Full parameter set for parallel trap pumping.
Full parameter set for serial trap pumping.
Charge injection followed by charge shuffling sequence.
Repeat 2x:
BIAS
VTP01
VTP02, 03, 04, dither
VTP05, 06, 07, 08, dither
VTP09, 10, 11, 12, dither
VTP01
VTP25, 26, 27, dither
VTP28, 29, 30, 31, dither
VTP32, 33, 34, 35, dither
VTP01
VTP47, 48, 49, dither
VTP50, 51, 52, 53, dither
VTP54, 55, 56, 57, dither
VTP01
VTP69, 70, 71, dither
VTP72, 73, 74, 75, dither
VTP76, 77, 78, 79, dither
Repeat 2x:
BIAS
VTP13
VTP14, 15, 16, dither
VTP17, 18, 19, 20, dither
VTP21, 22, 23, 24, dither
VTP13
VTP36, 37, 38, dither
VTP39, 40, 41, 42, dither
VTP43, 44, 45, 46, dither
VTP13
VTP58, 59, 60, dither
VTP61, 62, 63, 64, dither
VTP65, 66, 67, 68, dither
VTP13
VTP80, 81, 82, dither
VTP83, 84, 85, 86, dither
VTP87, 88, 89, 90, dither
Repeat 2x:
BIAS
STP01, 02, 03, 04, dither
STP05, 06, 07, 08, dither
STP09, 10, 11, 12, dither
Execute 3x throw-away BIASes
Fulfilling¶
Targets and pointing constraints¶
Pointing: Straylight suppression as per MOCDA-SYS-003.
Instrument configuration¶
Instrument: Wide survey
Methodology / Uplink procedure¶
Entity: VIS
Commanding Method: None
Dither Sequence: None
Inter-operability constraints¶
None
In-orbit duration¶
In-orbit Duration: 24.0 h + dither (x54)
Total time for parallel (96 full frames x 2 + Bias frame x 4): 20.7 h + dither (x48) [VTP total]
10.7 h + dither (x24) [VTP-CI-high]
10.0 h + dither (x24) [VTP-CI-low]
Note that 66s of the CDPU processing time can be accommodated into the dither/slew duration.
2 CI levels (DAC_IG1), 4 VSH modes, 11 TOI values (plus 8 ‘no pump’ frames), total 96 x 2 (VTP) + 4 (BIAS) = 196 frames. Different processing time for the two VTP variants; total running time is 21.3 h.
Longest TP sequence is 240s + 5s CI + 72s RO = 317s
Shortest TP sequence is 0.1s, i.e. 72s for readout + 5s flush
Limited by CDPU processing time: 315s (DAC_IG1=4V) and 290s (DAC_IG1=4.75V); + 20s buffer
2 x [(77s + 215s) (BIAS) + (72s+315s+20s) x 48] = 11.0 h(VTP-CI-high: DAC_IG1=4V)2 x [(77s + 215s) (BIAS) + (72s+290s+20s) x 48] = 10.3 h(VTP-CI-low: DAC_IG1=4.75V)
Total time for serial (12 frames + Bias frame x 1) x 2: 3.3h + dither (x6) [STP only]
CI levels, 2 SSH modes, 2 sets of TOI values, 3 sets of parameters: total 2x 12 (STP) + 2 (BIAS) = 26 frames.
STP post-processing is 15s, +15s buffer (includes 12 seconds for ROE soft reset)
(77s + 215s) * 5 (BIAS) + (445s + 30s) * 12 frames * 2 = 3.6 h
Data volume¶
96*VCH = 65280 MB (VTP) [VCH = VIS CI high (full frame) = 680MB compressed, S/C TVac data]
96*VCL = 58560 MB (VTP) [VCL = VIS CI low (full frame) = 610MB compressed, S/C TVac data]
24*VM = 9840 MB (STP) [VM = VIS Multi-STP (partial frame) = 410M compressed, linear interinterpolation from S/C TVac data]
9*VB = 2250 MB (BIAS)
Processing input¶
Parallel For each VMODE (x4) and CI level (x2), a set of 11 TOI_TP values to be used, plus a reference CI frame (zero shuffle) – doubled.
Serial For each Shuffle MODE (x2) and CI level (x2), 3 sets of configurations – doubled.
Data Description: Parallel 192 full frames in 4 different VMODE and CI level configurations
Serial 24 frames with 1220 lines
Processing method¶
VIS_CTI_TPCALIBRATE
Processing output¶
Position, emission time constant and pumping efficiency estimate of each detected trap.
Required accuracy, constraints¶
TBW
Processing tools¶
VIS_CTI_TPCALIBRATE
Validation¶
TBW
Recovery¶
ROE timeout error is generated for any serial trap pumping (STP) that lasts longer than 78 seconds. This error message indicates a failure in STP data acquisition.
The relevant limitation is as follows:
VIS-L-010: The readout phase in trap pumping sequences can last longer than the maximum readout time of 78s, which is hardcoded in CPDU FPGA, depending on the settings applied (number of lines, number of shuffles, dwell time, …). When this happens, the CDPU will report a ROE timeout error. If the limitation is not respected, the readout will be interrupted issuing the event ROE READOUT TIMEOUT (MIB ID 310152049), the sequences will be stopped with a 1,8 and the acquired data will be lost.
For STP sequences (serial trap pumping is a special form of readout), tt is necessary to make sure that the settings (specifically, the combination of NROWS, SER_DWELL and SHUFFLE) are compatible with the timeouts in the system. For the MSTP sequence, it is the individual STPs in the MSTP that must obey this readout duration upper limit.
Readout time = 4 * toi_image + SER_SHUFFLE *(t_rphi * 6 + SER_DWELL * 0.000000001) + t_rphi * 3 * NoSerialPixels) * NROWS
Where
SER_DWELL is in units of [ns]
toi_image = 0.000999 [seconds]
t_rphi = 0.00000475 [seconds]
NoSerialPixels = 2128
Quality control parameters¶
DataModel: https://gitlab.euclid-sgs.uk/
Contact person¶
VIS instrument scientist